{"id":1495,"date":"2025-01-05T15:54:00","date_gmt":"2025-01-05T15:54:00","guid":{"rendered":"https:\/\/www.pickplace.de\/?p=1495"},"modified":"2026-03-09T16:01:04","modified_gmt":"2026-03-09T16:01:04","slug":"cortex-m85-the-standard-for-ai-on-microcontrollers","status":"publish","type":"post","link":"https:\/\/www.pickplace.de\/en\/cortex-m85-der-standard-fur-ai-auf-mikrocontrollern\/","title":{"rendered":"Cortex M85 \u2013 the standard for AI on microcontrollers"},"content":{"rendered":"

Die Anforderungen an eingebettete Geräte sind in den letzten Jahren stark gestiegen. Besonders in Bereichen wie maschinellem Lernen (ML) und der Signalverarbeitung besteht ein wachsender Bedarf an leistungsfähigen und gleichzeitig energieeffizienten Lösungen. Durch begrenzte Ressourcen und Rechenleistung sind Mikrocontroller häufig nur zweite Wahl. Die kosten- und energieintensiveren High-End-Prozessoren wie Cortex-A oder spezialisierte GPU-basierte Ansätze stehen im Vordergrund. Nun jedoch preschen Hersteller mit der neuen Cortex-M85-Architektur vor.<\/p><\/div>\n\n\n\n

Mit dem ARM Cortex M85 steht nun ein neuer Standard für Mikrocontroller zur Verfügung, die speziell für die Anforderungen ressourcensparender mobiler Systeme entwickelt wurde. Der M85 kombiniert hohe deterministische Rechenleistung mit innovativen Features, die den Einsatz von MCUs über klassische Anwendungsfelder hinaus erweitern. Ferner sind ULP-Anwendungen (Ultra Low Power)  möglich. Die Grundlage für den im ML-Kontext benötigten hohen Datendurchsatz ist die Helium-Technologie, die durch die M-Profile Vector Extension (MVE) die Möglichkeit zu komplexeren Matrizenoperationen bietet.<\/p><\/div>\n\n\n\n

M-Profile Vector Extension (MVE)<\/h2><\/div>\n\n\n\n

A core component of the Cortex M85 is MVE, which massively increases processing speed for ML models and signal processing. ML applications at the edge often rely on optimized matrix operations that were previously trained on powerful servers and then implemented on microcontrollers. By utilizing libraries like CMSIS-NN, these models can be efficiently executed on the Cortex M.<\/p><\/div>\n\n\n\n

The Helium extension allows the Floating Point Unit (FPU) to be used as a 128-bit vector register, enabling 16 operations with 8-bit, 8 operations with 16-bit, or 4 operations with 32-bit to be performed in parallel. This results in up to four times the performance compared to a typical Cortex-M7 with similar performance parameters (clock, RAM\/ROM). Practically, microcontroller abstraction is provided via the CMSIS library. ARM thus provides the necessary MVE instructions directly with the CMSIS-NN library, which significantly simplifies the applicability of ML applications.<\/p><\/div>\n\n\n\n

The Helium technology of the Cortex M85 optimizes data processing through the concept of \u201ebeatwise\u201c execution, which is based on 8 vector registers, each with a length of 128 bits. These registers are divided into four equal sections of 32 bits each, referred to as \u201ebeats\u201c (A through D). Each beat represents 32 bits of computation, regardless of element size \u2013 for example, 1 x 32-bit MAC or 4 x 8-bit MAC.

A typical scenario, as illustrated in the following diagram, shows an alternating sequence of Vector Load (VLDR) and Vector MAC (VMLA) instructions over four clock cycles. In a classic 128-bit data path architecture, large portions of the hardware, such as the memory path and the MAC blocks, would often be underutilized. However, the MVE architecture breaks down each 128-bit-wide instruction into four equally sized beats. By separating the load and MAC hardware, the processing of these beats can be overlapped: while beat A of a VLDR is being loaded, beat A of a VMLA, which accesses data from the previous cycle, is simultaneously processed.<\/p><\/div>\n\n\n\n